Analog-to-Digital Converters (ADCs) play an important role in most modern signal processing and wireless communication systems where extensive signal manipulation is necessary to be performed by complicated digital signal processing (DSP) circuitry. This trend also creates the possibility of fabricating all functional blocks of a system in a single chip (System On Chip - SoC), with great reductions in cost, chip area and power consumption. However, this tendency places an increasing challenge, in terms of speed, resolution, power consumption, and noise performance, in the design of the front-end ADC which is usually the bottleneck of the whole system, especially under the unavoidable low supply-voltage imposed by technology scaling, as well as the requirement of battery operated portable devices. Generalized Low-Voltage Circuit Techniques for Very High-Speed Time-Interleaved Analog-to-Digital Converters will present new techniques tailored for low-voltage and high-speed Switched-Capacitor (SC) ADC with various design-specific considerations.

Detailed mathematical analysis in the various imperfections in the design of the data converters

Dedication. Preface. Acknowledgements. List of Abbreviations.1 Introduction. 2 Challenges in Low-Voltage Circuit Designs. 3 Advanced Low Voltage Circuit Techniques. 4 Time-Interleaving: Multiplying the Speed of the ADC. 5 Design of a 1.2V, 10-bit, 60-360MHz Time-Interleaved Pipelined ADC. 6 Experimental Results. 7 Conclusions and Prospective for Future Work. Appendix 1 Operation Principle of VG-CMFB with O-CMEC. Appendix 2 Mathematical Analysis of Bandwidth Mismatches. Appendix 3 Noise Analysis of Advanced Reset-Opamp Circuits. Appendix 4 Special Case in Gain mismatch.