Fast, Efficient and Predictable Memory Accesses presents techniques for designing fast, energy-efficient and timing predictable memory systems. By using a careful combination of compiler optimizations and architectural improvements, we can achieve more than what would be feasible at one of the levels in isolation. The described optimization algorithms achieve the goals of high performance and low energy consumption. In addition to these benefits, the use of scratchpad memories significantly improves the timing predictability of the entire system, leading to tighter worst case execution time bounds (WCET). The WCET is a relevant design parameter for all timing critical systems. In addition, the book covers algorithms to exploit the power down modes of main memories in SDRAM technology, as well as the execute-in-place feature of Flash memories. The final chapter considers the impact of the register file, which is also part of the memory hierarchy.

1 Abstract. 2 Introduction. 2.1 Motivation. 2.2 Contributions of this Work. 2.3 Overview. 3 Models and Tools. 3.1 Instruction Set Architecture Model. 3.2 Memory Models. 3.3 Timing Models. 3.4 Energy Models.3.5 Simulation Models. 3.6 The encc Compiler Framework. 4 Scratchpad Memory Optimizations. 4.1 Related Work. 4.2 Multi Memory Optimization. 4.3 Impact of Scratchpad Allocation Techniques on WCET. 5 Main Memory Optimizations. 5.1 Related Work. 5.2 Main Memory Power Management. 5.3 Execute-In-Place using Flash Memories. 6 Register File Optimization. 6.1 Related Work. 6.2 Implementation of the Register File. 6.3 Register Allocation and Lifetime Analysis. 6.4 Workflow and Methodology. 6.5 Benchmark Suite. 6.6 Compiler Guided Choice of Register File Size. 7 Summary. 8 Future Work. Index. References.