This book starts with background concerning three-dimensional integration - including their low energy consumption and high speed image processing - and then proceeds to how to construct them and which materials to use in particular situations. The book covers numerous applications, including next generation smart phones, driving assistance systems, capsule endoscopes, homing missiles, and many others. The book concludes with recent progress and developments in three dimensional packaging, as well as future prospects.

Gives instruction on how to build three-dimensional interconnects

Chapter 1 - Research and Development History of Three Dimensional (3D) Integration Technology1.1 Introduction1.1.1 The International Technology Roadmap for Semiconductors1.1.2 Three-dimensional Integration Technology1.2 Motivation for 3D Integration Technology y1.3 Research and Development History of 3D Integration Technology R&D History of 3D Packaging Technology1.3.1 3D Packaging Technology1.3.2 Origin of the TSV Concept1.3.3 Research and Development History of 3D Technology in Organizations1.3.3.1 Japan1.3.3.2 Japanese 3D Integration Technology Research and Development Project (Dream Chip)1.3.3.3 USA1.3.3.4 Europe1.3.3.5 Asia1.3.3.6 International1.4 Research and Development History of 3D Integration Technology for Applications1.4.1 CMOS Image Sensor and MEMS1.4.2 DRAM1.4.3 2.5D with Interposer1.4.4 OthersChapter 2- Recent Research and Development Activities of Three Dimensional (3D) Integration Technology2.1 Recent Announcement of Research and Development Activities2.2 Dynamic Random-Access Memory (DRAM)2.2.1 Through-Silicon Via (TSV) Technology for DRAM2.2.2 Wide I/O and Wide I/O2 Mobile DRAM2.3 Hybrid Memory Cube (HMC) and High Bandwidth Memory (HBM) DRAM2.3.1 Hybrid Memory Cube (HMC)High Bandwidth Memory (HBM) DRAM2.3.2 High Bandwidth Memory (HBM) DRAM2.4 FPGA and 2.5D2.5 Others2.6 New Energy and Industrial Technology Development Organization (NEDO) Japan2.6.1 Next Generation ¿Smart Device¿ Project2.6.2 Background, Purpose and Target of ¿Smart Device¿ ProjectChapter 3- TSV Processes3.1 Deep Silicon Etching by Bosch process3.1.1 Introduction3.1.2 Basic characteristics of the Bosch process3.1.3 Bosch Etching Equipment for TSV3.1.4 Conclusions3.2 High Rate Silicon-Via Etching and Basics of Sidewall Etch Reaction by Steady-State Etch Process3.2.1 Introduction3.2.2 MERIE Process for TSV Application3.2.2.1 Effect of RF Frequency3.2.2.2 Effect of Pressure3.2.2.3 Effect of Oxygen Addition3.2.3 Investigation of Sidewall Etch Reaction Induced by SF6/O2 Plasma3.2.3.1 Effect of Oxygen Addition3.2.3.2 Effect of Temperature3.2.3.3 Effect of SiF4 Addition3.2.4 Conclusion3.3 Low Temperature CVD Technology3.3.1 Introduction3.3.2 Cathode-Coupled PECVD (LS-CVD)3.3.3 Low Temperature SiO2 Deposition3.3.3.1 Wafer Temperature During Low Temperature Deposition3.3.3.2 Step Coverage in Si Via Holes3.3.3.3 Electrical Characteristics of SiO2 Film Deposited at Low Temperature3.3.3.4 Stress Control of SiO2 Film Deposited Using LS-CVD3.3.4 Conclusion3.4 Electrodeposition for Via-Filling3.4.1 Cu+ Ion as an Accelerant Additive of Copper Electrodeposition3.4.2 Relation between via Filling and Cu+ Ion by Periodical Reverse Current Waveform3.4.3 Simulation of Cu+ Ion Distribution inside the Via3.4.4 High Speed via Filling Electrodeposition by Other Organizations3.4.5 Reduction of Thermal Expansion Coefficient of Electrodeposited Copper for TSV by AdditiveChapter 4 - Wafer Handling and Thinning Processes4.1 Wafer Thinning Solution for TSV Devices4.1.1 Introduction4.1.2 General Thinning4.1.3 Wafer Thinning for TSV devices4.1.4 TTV control4.1.5 Summary4.2 A Novel Via Middle TSV Thinning Technology by Si/Cu Grinding and CMP4.2.1 Introduction4.2.2 Methods4.2.3 Results and Discussion4.2.3.1 Si/Cu Same Rate CMP (1st CMP)4.2.3.2 TSV Protrusion CMP (2nd CMP)4.2.3.3 Post CMP Cleaning after 2nd CMP4.2.4 Conclusion4.3 Temporally Bonding4.3.1 Background4.3.2 The 3MTM Temporary Bonding Materials4.3.3 The 3MTM Temporary Adhesive4.3.4 Laser Absorbing Layer4.3.5 The Next Steps4.4 Temporary Bonding and Debonding for Through-Silicon Via (TSV) Processing4.4.1 Introduction4.4.2 Temporary Bonding and Debonding Process4.4.3 Debonding Method4.4.4 Functions and Performance Requirements for Temporary Bonding Device4.4.5 Ability and Performance Requirements for Debonding Devices4.4.6 Tokyo Electron¿s Temporary Bonder and Debonder Device Concept and Lineup4.4.7 Future OutlookChapter 5- Wafer and Die Bonding Processes5.1 Permanent Wafer Bonding5.1.1 Introduction5.1.2 Low Temperature or Room Temperature Wafer Direct Bonding Method and Application5.1.2.1 Fusion Bonding5.1.2.2 Surface Activated Bonding5.1.2.3 Anodic Bonding5.1.2.4 Cu2Cu/Oxide Hybrid bonding5.1.2.5 Conclusion of Low Temperature or Room Temperature Wafer Direct Bonding Methods and Their Applications5.1.2.6 Future Outlook for Bonding Application Using Low Temperature or Normal Room Temperature Wafer Direct Bonding Methods5.1.3 Requests Made to Equipment Makers and Initiatives Regarding Low Temperature or Room Temperature Wafer Direct Bonding Methods5.1.3.1 Post BAA5.1.3.2 Scaling5.1.3.3 Distortion5.1.3.4 Bonding strength5.1.3.5 Void5.1.4 Tokyo Electron Initiatives5.1.5 Conclusion5.2 Underfill Materials5.2.1 Technical Trend for Three Dimensional Integration Packages and Underfill Materials5.2.2 Requirements for Underfill Materials5.2.2.1 Requirements for CUF and Material Technology Trend5.2.2.2 Requirements for NCP and Material Technology Trend5.2.3 Application to CUF between the Stacked Chips5.3 Non-Conductive Films5.3.1 Introduction5.3.2 Required Material Feature from Bonding Process5.3.3 Voiding Issue in NC5.3.4 High Through Put NCF-TCBChapter 6- Metrology and Inspection6.1 Principles of Spectroscopic Reflectometry6.1.1 Introduction6.1.2 Measurement6.1.3 Setup6.1.4 Analysis6.1.5 Conclusion6.2 Low Coherence Interferometry for 3D-IC TSV6.2.1 Optical Measurement of Topographies and Thicknesses6.2.1.1 3D-IC TSV Needs Tomography6.2.1.2 Tomography with Low Coherence Interferometry6.2.2 Theory of Optical Coherence Tomography6.2.2.1 Basic Principle6.2.2.2 Time Domain OCT6.2.2.3 Fourier Domain OCT6.2.3 Practical Considerations6.2.4 Conclusion6.3 Silicon and Glue Thickness Measurement for Grinding6.3.1 Introduction6.3.2 TSV Wafer Manufacturing Method and Challenges of Grinding6.3.3 Features of BGM3006.3.4 Verifying BGM300 Measurement Results6.3.5 Measurement after Grinding6.3.6 Optimized wafer Grinding Based on Via Height Information from BGM3006.3.7 Conclusion6.4 3D X-ray Microscopy Technology for Non-Destructive Analysis of Through-Silicon Vias6.4.1 Introduction6.4.2 Fundamentals of X-ray Microscopy6.4.2.1 Physics of X-ray Imaging6.4.2.2 3D X-ray Microscopy6.4.3 Applications for TSV Process Development6.4.4 Applications for TSV Failure Analysis6.4.5 Summary6.5 Wafer Warpage and Local Distortion Measurement6.5.1 Introduction6.5.2 Basic Functions of WDM3006.5.3 Measurement and Analysis of Local Deformations6.5.4 Application6.5.5 SummaryChapter 7 - TSV Characteristics and Reliability: Impact of 3D Integration Processes on Device Reliability7.1 Introduction7.2 Impact of Cu Contamination on Device Reliabilities in Thinned 3D-IC Chip7.2.1 Impact of Cu Diffusion at Backside Surface in Thinned 3D-IC Chip7.2.1.1 Effect of Intrinsic Gettering (IG) layer7.2.1.2 Effect of Extrinsic Gettering (EG) layer7.2.2 Impact of Cu Diffusion from Cu Via7.2.2.1 Effect of the Barrier Thickness and the Scallop Roughness7.2.2.2 Effect of the Annealing Temperature7.2.2.3 Keep Out Zone (KOZ) Characterization by Cu Diffusion from Cu Via7.3 Impact of Mechanical Stress/Strain on Device Reliability in Stacked IC7.3.1 Micro-Bump Induced Local Stress in Stacked IC7.3.2 Si Mechanical Strength Reduction by Thinning7.4 Impact of 3D Integration Process on DRAM Retention Characteristics7.4.1 Impact of Mechanical Strength on Retention Characteristics in Thinn DRAM Chip7.4.2 Impact of Cu Contamination on Memory Retention Characteristics in DRAM ChipChapter 8 - Trends in 3D Integrated Circuit (3D-IC) Testing Technology8.1 Crucial Issues and Key Technologies for 3D-IC Testing8.2 Research Trends in Pre-bond Test for 3D-IC8.3 Research Trends in Post-bond Test for 3D-IC8.4 Research Trends in Automatic Test Pattern Generator (ATPG) and Test Scheduling for TSVs in 3D-IC8.5 An Accurate Resistance Measuring Method for TSVs in 3D-IC8.5.1 Background of Our Study8.5.2 Problems of Conventional Analog Boundary-Scan for TSV Resistance Measurement8.5.2.1 Analog Boundary-Scan8.5.2.2 Standard resistance measuring method by 1149.48.5.2.3 Problems of conventional Analog Boundary-Scan for TSV resistance measuring8.5.3 Proposed Measuring Method8.5.3.1 Floating Measurement method8.5.3.2 Complete isolation of the current path and the voltage path8.5.3.3 Segmenting the internal analog BUS (AB1, AB2)8.5.4 Summary8.6 Delay Measurement Circuits for Detecting TSV Delay Faults8.6.1 Application of Time-to-Digital Converter Embedded in Boundary-Scan for 3D-IC Testing8.6.2 Delay Measurement Circuit Using the Vernier Delay Line8.6.3 Estimation of Defect Size Detectable by the Test Method8.6.4 Summary8.7 Electrical Interconnect Tests of Open Defects in a 3D-IC with a Built-in Supply Current Test Circuit8.7.1 Electrical Tests with a Built-in Supply Current Test Circuit8.7.2 Experimental Evaluation of Our Electrical Test Method8.7.3 SummaryChapter 9 - Dream Chip Project at ASET9.1 Overview of Japanese 3D Integration Technology R&D Project (Dream Chip)9.2 Thermal Management and Chip Stacking Technology9.2.1 Background9.2.2 Chip Stacking/Joining Technology9.2.2.1 Metal Bump Materials and Structure9.2.2.2 Reliability Study of Micro Bump9.2.2.3 Electro Migration Test to Understand Current Density of Micro Bump Joint9.2.2.4 Flip Chip Bonding Density Towards 10 ¿m Connection Bump Pitch9.2.2.5 Stack and Gang Bonding9.2.2.6 Non-destructive Inspection Technologies of Micro Joint9.2.3 Thermal Management Study9.2.3.1 Evaluation Technology of 3D Integrated Chip Stack9.2.3.2 TV200 Measurement Result and Correlation with Simulation9.2.3.3 Thermal Conductivity Anisotropy Induced by Cu TSV9.2.4 Development of Automobile Drive Assistance Camera9.2.4.1 Development of Integration Process9.2.4.2 Development of Cooling System for Automobile Drive Assistance Camera9.2.5 Summery9.3 Thin Wafer Technology9.3.1 Back Ground of Wafer Thinning Technology9.3.2 Issues of Wafer Thinning9.3.3 Ultrathin Wafer Thinning Process9.3.3.1 Wafer Support System (WSS)9.3.3.2 Thermal Resistance of the Resin Used for WSS Temporary Bonding9.3.3.3 Dicing Technology of Thin Chip9.3.3.4 Die Pick-up Technology of Thin Chip9.3.3.5 Thin Wafer Processing Technique in the Wafer Stacking Process9.3.4 Issues on Wafer Thinning to Prevent Device Characteristics Change and Metal Contamination9.3.4.1 Evaluation Method of a Crystal Defect and Metal Pollution in the Thin Wafer9.3.4.2 Backside Grinding Methods and Their EG Effect9.3.4.3 Electrical Characteristics Deviation by Mechanical Stress9.3.5 Standardization9.3.6 Summary9.4 3D Integration Technology9.4.1 Background and Scope9.4.2 C2C Process9.4.2.1 C2C Integration Overview9.4.2.2 C2C Integration Results9.4.3 W2W Process9.4.3.1 W2W Integration Overview9.4.3.2 Wafer Bonding Technology9.4.3.3 W2W Integration Results9.4.4 Summary9.5 Ultra-wide Bus 3D-System-in Package (3D-SiP) Technology9.5.1 Background9.5.2 The Test Vehicle Fabrication9.5.3 Evaluation9.5.4 Summary9.6 Mixed Signal (Digital and Analog) 3D Integration Technology for Automotive Application9.6.1 Introduction9.6.2 Challenges9.6.3 Result of Basic Technology Development on Mixed-Signal 3D Integration Technology9.6.3.1 Basic Technology Development on 3D Integrated Imaging Sensor Module for In-Vehicle9.6.3.2 Realization of Mixed-Signal (CIS/CDS/ADC/IF) Integrated Structure by TSV Connection9.6.3.3 Development of Si Interposer Which Allotted TSV Type Decoupling Capacitor9.6.3.4 A Trial production and Evaluation of Car Drive Assist Image Processing System for Cars9.6.4 Conclusion9.7 Heterogeneous 3D Integration Technology for Radio Frequency Micro Electro Mechanical Systems RF MEMS (RF MEMS)9.7.1 Background and Issues9.7.2 Development Result9.7.2.1 Structure of 3D integration RF Module9.7.2.2 MEMS Tunable Filter9.7.2.3 MEMS Switch9.7.2.4 CMOS Driving IC9.7.2.5 3D Integration of Tunable Filter Module9.7.2.6 RF and Tuning Performances of the Fabricated 3D Tunable Filter Module9.7.3 Summary