Fundamentals of IP and SoC Security

Design, Verification, and Debug
 HC runder Rücken kaschiert

144,06 €*

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ISBN-13:
9783319500553
Veröffentl:
2017
Einband:
HC runder Rücken kaschiert
Erscheinungsdatum:
01.02.2017
Seiten:
324
Autor:
Swarup Bhunia
Gewicht:
653 g
Format:
241x160x24 mm
Sprache:
Englisch
Beschreibung:

This book is about security in embedded systems and it provides an authoritative reference to all aspects of security in system-on-chip (SoC) designs. The authors discuss issues ranging from security requirements in SoC designs, definition of architectures and design choices to enforce and validate security policies, and trade-offs and conflicts involving security, functionality, and debug requirements. Coverage also includes case studies from the ¿trenches¿ of current industrial practice in design, implementation, and validation of security-critical embedded systems. Provides an authoritative reference and summary of the current state-of-the-art in security for embedded systems, hardware IPs and SoC designs;Takes a "cross-cutting" view of security that interacts with different design and validation components such as architecture, implementation, verification, and debug, each enforcing unique trade-offs;Includes high-level overview, detailed analysis on implementation, and relevant case studies on design/verification/debug issues related to IP/SoC security.
Provides an authoritative reference and summary of the current state-of-the-art in security for embedded systems, hardware IPs and SoC designs;
Introduction.- Security Validation.- SoC Security and Debug.- IP Trust: The Problem and Design/Validation based Solution.- Security of Crypto IP Core: Issues and Countermeasures.- PUF-Based Authentication.- FPGA-based IP and SoC Security.- Physical Unclonable Functions and Intellectual Property Protection Techniques.- A Systematic Approach to Fault-Attack Resistant Design.- Hardware Trojan Attacks and Countermeasures.- In-place Logic Obfuscation for Emerging Nonvolatile FPGAs.- Security Standards for Embedded Devices and Systems.- Conclusion.

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