The Dark Side of Silicon

Energy Efficient Computing in the Dark Silicon Era
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ISBN-13:
9783319315942
Veröffentl:
2017
Einband:
HC runder Rücken kaschiert
Erscheinungsdatum:
09.01.2017
Seiten:
356
Autor:
Amir M. Rahmani
Gewicht:
699 g
Format:
241x160x25 mm
Sprache:
Englisch
Beschreibung:

This book presents the state-of-the art of one of the main concerns with microprocessors today, a phenomenon known as "dark silicon". Readers will learn how power constraints (both leakage and dynamic power) limit the extent to which large portions of a chip can be powered up at a given time, i.e. how much actual performance and functionality the microprocessor can provide. The authors describe their research toward the future of microprocessor development in the dark silicon era, covering a variety of important aspects of dark silicon-aware architectures including design, management, reliability, and test. Readers will benefit from specific recommendations for mitigating the dark silicon phenomenon, including energy-efficient, dedicated solutions and technologies to maximize the utilization and reliability of microprocessors.
Enables readers to understand the dark silicon phenomenon and why it has emerged, including detailed analysis of its impacts;
Introduction.- Dark vs. Dim Silicon and Near-Threshold Computing.- The SiLago Solution: Architecture and Design Methods for a Heterogeneous Dark Silicon aware Coarse Grain Reconfigurable Fabric.- Heterogeneous Dark Silicon Chip Multi-Processors Design and Run-time Management.- Thermal Safe Power (TSP) - Efficient Thermal-Aware Power Budgeting for Manycore Systems in Dark Silicon.- Power Management of Asymmetric Multi-Cores in the Dark Silicon Era.- Multi-Objective Power Management for CMPs in the Dark Silicon Age.- Robust Application Scheduling with Adaptive Parallelism in Dark-Silicon Constrained Multicore Systems.- Dark Silicon Patterning: Ef¿cient Power Utilization through Run-time Mapping.- Online Software-Based Self-Testing in the Dark Silicon Era.- Adroit Use of Dark Silicon for Power, Performance and Reliability Optimization of NoCs.- NoC-aware Computational Sprinting.

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