Beschreibung:
New manufacturing technologies have made possible the integration of entire systems on a single chip. This new design paradigm, termed system-on-chip (SOC), together with its associated manufacturing problems, represents a real challenge for designers.
The reader will learn about the state of the art in system-level validation and test procedures which will enhance both the reliability and performance of system on chip designs
Modeling Permanent Faults.- Test Generation: A Symbolic Approach.- Test Generation: A Heuristic Approach.- Test Generation: A Hierarchical Approach.- Test Program Generation from High-level Microprocessor Descriptions.- Tackling Concurrency and Timing Problems.- An Approach to System-level Design for Test.- System-level Dependability Analysis.