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Test Resource Partitioning for System-on-a-Chip
ISBN-13:
9781461511137
Veröffentl:
2012
Seiten:
232
Autor:
Vikram Iyengar
Serie:
20, Frontiers in Electronic Testing
eBook Typ:
PDF
eBook Format:
EPUB
Kopierschutz:
1 - PDF Watermark
Sprache:
Englisch
Beschreibung:
Test Resource Partitioning for System-on-a-Chip is about test resource partitioning and optimization techniques for plug-and-play system-on-a-chip (SOC) test automation. Plug-and-play refers to the paradigm in which core-to-core interfaces as well as core-to-SOC logic interfaces are standardized, such that cores can be easily plugged into "virtual sockets" on the SOC design, and core tests can be plugged into the SOC during test without substantial effort on the part of the system integrator. The goal of the book is to position test resource partitioning in the context of SOC test automation, as well as to generate interest and motivate research on this important topic.
1. Test Resource Partitioning.- 2. Test Access Mechanism Optimization.- 3. Improved Test Bus Partitioning.- 4. Test Wrapper And TAM Co-Optimization.- 5. Test Scheduling.- 6. Precedence, Preemption, And Power Constraints.- 7. Test Data Compression Using Golomb Codes.- 8. Frequency-Directed Run-Length (FDR) Codes.- 9. TRP for Low-Power Scan Testing.- 10. Conclusion.- References.
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