This book describes a system of VLSI layout tools called IDA which stands for "Integrated Design Aides. " It is not a main-line production CAD environment, but neither is it a paper tool. Rather, IDA is an experimental environment that serves to test out CAD ideas in the crucible of real chip design. Many features have been tried in IDA over the years, some successfully, some not. This book will emphasize the former, and attempt to describe the features that have been useful and effective in building real chips. Before discussing the present state of IDA, it may be helpful to understand how the project got started. Although Bell Labs has traditionally had a large and effective effort in VLSI and CAD, researchers at the Murray Hill facility wanted to study the process of VLSI design independently, emphasizing the idea of small team chip building. So, in 1979 they invited Carver Mead to present his views on MOS chip design, complete with the now famous "lambda" design rules and "tall, thin designers. " To support this course, Steve Johnson (better known for YACC and the portable C compiler) and Sally Browning invented the constraint­ based "i" language and wrote a compiler for it. A small collection of layout tools developed rapidly around this compiler, including design rule checkers, editors and simulators.

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1: Introduction.- 2: The IMAGES Language.- 2.1 Background.- 2.2 Principal Constructs.- 2.3 Geometric Constraints.- 2.4 Geometric Constraint Resolution.- 2.5 Electrical Connectivity.- 2.6 Other IMAGES Features.- 2.7 Interface with the Rest of IDA.- 2.8 Quick Access to Large Designs.- 2.9 The IMAGES Implementation.- 2.10 Summary.- 3: Designer Interaction.- 3.1 Basic Editing Environment.- 3.2 Hybrid Logic/Layout Diagrams.- 3.3 Interactive Simulation.- 3.4 Compaction.- 3.5 Reading from the Top-Down.- 3.6 Editor Internals.- 3.7 Moving on - Icon as a Non-graphical Tool.- 4: Geometric Algorithms.- 4.1 Enhancing the Basic IMAGES Data Structures.- 4.2 Scan-Line Technique.- 4.3 Consolidating Rectangles.- 4.4 Tub Insertion.- 4.5 Hierarchical Net Extraction.- 4.6 Hierarchical Design Rule Checking.- 4.7 Summary.- 5: Enhancements to the IMAGES Language for Synthesis.- 5.1 Stretchable Routing using IMAGES Constraints.- 5.2 Impact on Design Methods.- 5.3 Designer Written "Generators".- 5.4 Design Rule Undatable Generators.- 5.5 Summary: Advantages and Limitations.- 6: Automatic Layout of Switch-Level Designs.- 6.1 System Organization.- 6.2 Steps in SC2D.- 6.3 Steps After SC2D.- 6.4 Detailed Layout in SC2.- 6.5 Performance and Parallel Processing.- 6.6 Summary.- 7: Switch-Level Tools.- 7.1 Transistor Sizing with TILOS.- 7.2 SLICC - An Alternative to Schematics.- 8: Summary and Trends.- 8.1 Summary.- 8.2 VLSI: From Science Fiction to Commodity.- 8.3 Design Style Trends.- Appendix A: Data Structures.- A.1 Basic IDA Data Structures.- A.2 Basic Design Elements.- Appendix B: Background on the "i" Language.- References.