Designing Reliable and Efficient Networks on Chips
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ISBN-13:
9781402097560
Veröffentl:
2009
Erscheinungsdatum:
21.04.2009
Seiten:
198
Autor:
Srinivasan Murali
Gewicht:
459 g
Format:
244x165x20 mm
Sprache:
Englisch
Beschreibung:
Developing NoC based interconnect tailored to a particular application domain, satisfying the application performance constraints with minimum power-area overhead is a major challenge. With technology scaling, as the geometries of on-chip devices reach the physical limits of operation, another important design challenge for NoCs will be to provide dynamic (run-time) support against permanent and intermittent faults that can occur in the system. The purpose of Designing Reliable and Efficient Networks on Chips is to provide state-of-the-art methods to solve some of the most important and time-intensive problems encountered during NoC design.
First book that presents in depth the state-of-the-art algorithms and optimization models for performing system-level design of NoCs
NoC Design Methods.- Designing Crossbar Based Systems.- Netchip Tool Flow for NoC Design.- Designing Standard Topologies.- Designing Custom Topologies.- Supporting Multiple Applications.- Supporting Dynamic Application Patterns.- NoC Reliability Mechanisms.- Timing-Error Tolerant NoC Design.- Analysis of NoC Error Recovery Schemes.- Fault-Tolerant Route Generation.- NoC Support for Reliable On-Chip Memories.- Conclusions and Future Directions.
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