ANALYSIS AND DESIGN OF ANALOG INTEGRATED CIRCUITS Authoritative and comprehensive textbook on the fundamentals of analog integrated circuits, with learning aids included throughout Written in an accessible style to ensure complex content can be appreciated by both students and professionals, this Sixth Edition of Analysis and Design of Analog Integrated Circuits is a highly comprehensive textbook on analog design, offering in-depth coverage of the fundamentals of circuits in a single volume. To aid in reader comprehension and retention, supplementary material includes end of chapter problems, plus a Solution Manual for instructors. In addition to the well-established concepts, this Sixth Edition introduces a new super-source follower circuit and its large-signal behavior, frequency response, stability, and noise properties. New material also introduces replica biasing, describes and analyzes two op amps with replica biasing, and provides coverage of weighted zero-value time constants as a method to estimate the location of dominant zeros, pole-zero doublets (including their effect on settling time and three examples of circuits that create doublets), the effect of feedback on pole-zero doublets, and MOS transistor noise performance (including a thorough treatment on thermally induced gate noise). Providing complete coverage of the subject, Analysis and Design of Analog Integrated Circuits serves as a valuable reference for readers from many different types of backgrounds, including senior undergraduates and first-year graduate students in electrical and computer engineering, along with analog integrated-circuit designers.

Chapter 1 Models for Integrated-Circuit Active Devices 11.1 Introduction 11.2 Depletion Region of a pn Junction 11.2.1 Depletion-Region Capacitance 51.2.2 Junction Breakdown 71.3 Large-Signal Behavior of Bipolar Transistors 91.3.1 Large-Signal Models in the Forward-Active Region 91.3.2 Effects of Collector Voltage on Large-Signal Characteristics in the Forward-Active Region 141.3.3 Saturation and Inverse-Active Regions 161.3.4 Transistor Breakdown Voltages 211.3.5 Dependence of Transistor Current Gain ß F on Operating Conditions 241.4 Small-Signal Models of Bipolar Transistors 261.4.1 Transconductance 261.4.2 Base-Charging Capacitance 281.4.3 Input Resistance 291.4.4 Output Resistance 301.4.5 Basic Small-Signal Model of the Bipolar Transistor 301.4.6 Collector-Base Resistance 311.4.7 Parasitic Elements in the Small-Signal Model 311.4.8 Specification of Transistor Frequency Response 351.5 Large-Signal Behavior of Metal-Oxide-Semiconductor Field-Effect Transistors 391.5.1 Transfer Characteristics of MOS Devices 391.5.2 Comparison of Operating Regions of Bipolar and MOS Transistors 461.5.3 Decomposition of Gate-Source Voltage 481.5.4 Threshold Temperature Dependence 481.5.5 MOS Device Voltage Limitations 491.6 Small-Signal Models of MOS Transistors 501.6.1 Transconductance 511.6.2 Intrinsic Gate-Source and Gate-Drain Capacitance 521.6.3 Input Resistance 531.6.4 Output Resistance 531.6.5 Basic Small-Signal Model of the MOS Transistor 531.6.6 Body Transconductance 541.6.7 Parasitic Elements in the Small-Signal Model 551.6.8 MOS Transistor Frequency Response 571.7 Short-Channel Effects in MOS Transistors 601.7.1 Velocity Saturation from the Horizontal Field 601.7.2 Transconductance and Transition Frequency 641.7.3 Mobility Degradation from the Vertical Field 661.8 Weak Inversion in MOS Transistors 671.8.1 Drain Current in Weak Inversion 671.8.2 Transconductance and Transition Frequency in Weak Inversion 701.9 Substrate Current Flow in MOS Transistors 73A.1.1 Summary of Active-Device Parameters 74Problems 76References 78General References 79Chapter 2 Bipolar, MOS, and BiCMOS Integrated-Circuit Technology 812.1 Introduction 812.2 Basic Processes in Integrated-Circuit Fabrication 822.2.1 Electrical Resistivity of Silicon 822.2.2 Solid-State Diffusion 832.2.3 Electrical Properties of Diffused Layers 852.2.4 Photolithography 872.2.5 Epitaxial Growth 892.2.6 Ion Implantation 902.2.7 Local Oxidation 902.2.8 Polysilicon Deposition 902.3 High-Voltage Bipolar Integrated-Circuit Fabrication 912.4 Advanced Bipolar Integrated-Circuit Fabrication 952.5 Active Devices in Bipolar Analog Integrated Circuits 982.5.1 Integrated-Circuit npn Transistors 992.5.2 Integrated-Circuit pnp Transistors 1112.6 Passive Components in Bipolar Integrated Circuits 1182.6.1 Diffused Resistors 1192.6.2 Epitaxial and Epitaxial-Pinch Resistors 1222.6.3 Integrated-Circuit Capacitors 1242.6.4 Zener Diodes 1242.6.5 Junction Diodes 1252.7 Modifications to the Basic Bipolar Process 1272.7.1 Dielectric Isolation 1272.7.2 Compatible Processing for High-Performance Active Devices 1282.7.3 High-Performance Passive Components 1312.8 MOS Integrated-Circuit Fabrication 1312.9 Active Devices in MOS Integrated Circuits 1352.9.1 n-Channel Transistors 1352.9.2 p-Channel Transistors 1482.9.3 Depletion Devices 1482.9.4 Bipolar Transistors 1492.10 Passive Components in MOS Technology 1502.10.1 Resistors 1502.10.2 Capacitors in MOS Technology 1522.10.3 Latchup in CMOS Technology 1552.11 BiCMOS Technology 1562.12 Heterojunction Bipolar Transistors 1572.13 Interconnect Delay 1602.14 Economics of Integrated-Circuit Fabrication 1602.14.1 Yield Considerations in Integrated-Circuit Fabrication 1612.14.2 Cost Considerations in Integrated-Circuit Fabrication 163A.2.1 Spice Model-Parameter Files 166Problems 167References 170Chapter 3 Single-Transistor and Multiple-Transistor Amplifiers 1733.1 Device Model Selection for Approximate Analysis of Analog Circuits 1743.2 Two-Port Modeling of Amplifiers 1753.3 Basic Single-Transistor Amplifier Stages 1773.3.1 Common-Emitter Configuration 1783.3.2 Common-Source Configuration 1823.3.3 Common-Base Configuration 1863.3.4 Common-Gate Configuration 1893.3.5 Common-Base and Common-Gate Configurations with Finite r o 1913.3.6 Common-Collector Configuration (Emitter Follower) 1953.3.7 Common-Drain Configuration (Source Follower) 1983.3.8 Common-Emitter Amplifier with Emitter Degeneration 2013.3.9 Common-Source Amplifier with Source Degeneration 2043.4 Multiple-Transistor Amplifier Stages 2063.4.1 The CC-CE, CC-CC, and Darlington Configurations 2063.4.2 The Cascode Configuration 2103.4.3 The Active Cascode 2143.4.4 The Super Source Follower 2163.5 Differential Pairs 2193.5.1 The dc Transfer Characteristic of an Emitter-Coupled Pair 2193.5.2 The dc Transfer Characteristic with Emitter Degeneration 2213.5.3 The dc Transfer Characteristic of a Source-Coupled Pair 2223.5.4 Introduction to the Small-Signal Analysis of Differential Amplifiers 2253.5.5 Small-Signal Characteristics of Balanced Differential Amplifiers 2283.5.6 Device Mismatch Effects in Differential Amplifiers 235A.3.1 Elementary Statistics and the Gaussian Distribution 250Problems 253References 257Chapter 4 Current Mirrors, Active Loads, and References 2594.1 Introduction 2594.2 Replica Biasing 2594.3 Current Mirrors 2614.3.1 General Properties 2614.3.2 Simple Current Mirror 2634.3.3 Simple Current Mirror with Beta Helper 2694.3.4 Simple Current Mirror with Degeneration 2704.3.5 Cascode Current Mirror 2724.3.6 Wilson Current Mirror 2834.4 Active Loads 2874.4.1 Motivation 2874.4.2 Common-Emitter-Common-Source Amplifier with Complementary Load 2884.4.3 Common-Emitter-Common-Source Amplifier with Depletion Load 2914.4.4 Common-Emitter-Common-Source Amplifier with Diode-Connected Load 2934.4.5 Differential Pair with Current-Mirror Load 2964.5 Voltage and Current References 3094.5.1 Low-Current Biasing 3094.5.2 Supply-Insensitive Biasing 3154.5.3 Temperature-Insensitive Biasing 327A.4.1 Matching Considerations in Current Mirrors 338A.4.1.1 Bipolar 338A.4.1.2 Mos 340A.4.2 Input Offset Voltage of a Differential Pair with Active Load 343A.4.2.1 Bipolar 343A.4.2.2 Mos 345Problems 348References 353Chapter 5 Output Stages 3555.1 Introduction 3555.2 The Emitter Follower as an Output Stage 3555.2.1 Transfer Characteristics of the Emitter-Follower 3565.2.2 Power Output and Efficiency 3595.2.3 Emitter-Follower Drive Requirements 3665.2.4 Small-Signal Properties of the Emitter Follower 3665.3 The Source Follower as an Output Stage 3685.3.1 Transfer Characteristics of the Source Follower 3685.3.2 Distortion in the Source Follower 3705.3.3 Transfer Characteristics of the Super Source Follower 3745.4 Class B Push-Pull Output Stage 3785.4.1 Transfer Characteristic of the Class B Stage 3785.4.2 Power Output and Efficiency of the Class B Stage 3815.4.3 Practical Realizations of Class B Complementary Output Stages 3855.4.4 All-npn Class B Output Stage 3925.4.5 Quasi-Complementary Output Stages 3945.4.6 Overload Protection 3975.5 CMOS Class AB Output Stages 3995.5.1 Common-Drain Configuration 3995.5.2 Common-Source Configuration with Error Amplifiers 4015.5.3 Alternative Configurations 408Problems 415References 420Chapter 6 Operational Amplifiers with Single-Ended Outputs 4216.1 Applications of Operational Amplifiers 4226.1.1 Basic Feedback Concepts 4226.1.2 Inverting Amplifier 4236.1.3 Noninverting Amplifier 4256.1.4 Differential Amplifier 4256.1.5 Nonlinear Analog Operations 4266.1.6 Integrator, Differentiator 4276.1.7 Internal Amplifiers 4286.2 Deviations from Ideality in Real Operational Amplifiers 4366.2.1 Input Bias Current 4376.2.2 Input Offset Current 4376.2.3 Input Offset Voltage 4386.2.4 Common-Mode Input Range 4386.2.5 Common-Mode Rejection Ratio (cmrr) 4396.2.6 Power-Supply Rejection Ratio (psrr) 4406.2.7 Input Resistance 4416.2.8 Output Resistance 4426.2.9 Frequency Response 4426.2.10 Operational-Amplifier Equivalent Circuit 4426.3 Basic Two-Stage MOS Operational Amplifiers 4436.3.1 Input Resistance, Output Resistance, and Open-Circuit Voltage Gain 4446.3.2 Output Swing 4466.3.3 Input Offset Voltage 4466.3.4 Common-Mode Rejection Ratio 4506.3.5 Common-Mode Input Range 4516.3.6 Power-Supply Rejection Ratio (psrr) 4536.3.7 Effect of Overdrive Voltages 4586.3.8 Layout Considerations 4596.3.9 Amplifier with Level Shifting in the Input Stage 4626.4 Two-Stage MOS Operational Amplifiers with Cascodes 4656.5 MOS Folded-Cascode Operational Amplifiers 4676.6 MOS Telescopic-Cascode Operational Amplifiers 4716.7 Replica Biasing of the Tail Current Source 4756.8 MOS Active-Cascode Operational Amplifiers 489Problems 492References 498Chapter 7 Frequency Response of Integrated Circuits 4997.1 Introduction 4997.2 Single-Stage Amplifiers 4997.2.1 Single-Stage Voltage Amplifiers and the Miller Effect 4997.2.2 Frequency Response of the Common-Mode Gain for a Differential Amplifier 5117.2.3 Frequency Response of Voltage Buffers 5137.2.4 Frequency Response of Current Buffers 5277.3 Multistage Amplifier Frequency Response 5317.3.1 Dominant-Pole Approximation 5317.3.2 Zero-Value Time Constant Analysis 5327.3.3 Cascade Voltage-Amplifier Frequency Response 5377.3.4 Cascode Frequency Response 5417.3.5 Frequency Response of a Current Mirror Loading a Differential Pair 5487.3.6 Short-Circuit Time Constants 5497.3.7 Weighted Zero-Value Time Constants 5547.4 Relation Between Frequency Response and Time Response 5637.5 Pole-Zero Doublets 5657.5.1 Effect of a Pole-Zero Doublet on Settling Time 5657.5.2 Frequency Dependence of a Cascode Current-Source Load 5707.5.3 Frequency Dependence of an Active-Cascode Current-Source Load 5727.5.4 Doublet in a Differential Amplifier with Mismatch 574Problems 575References 584Chapter 8 Feedback 5858.1 Ideal Feedback Equation 5858.2 Gain Sensitivity 5878.3 Effect of Negative Feedback on Distortion 5878.4 Feedback Configurations 5898.4.1 Series-Shunt Feedback 5898.4.2 Shunt-Shunt Feedback 5928.4.3 Shunt-Series Feedback 5948.4.4 Series-Series Feedback 5958.5 Practical Configurations and the Effect of Loading 5958.5.1 Shunt-Shunt Feedback 5968.5.2 Series-Series Feedback 6028.5.3 Series-Shunt Feedback 6118.5.4 Shunt-Series Feedback 6178.5.5 Summary 6208.6 Single-Stage Feedback 6208.6.1 Local Series-Series Feedback 6228.6.2 Local Series-Shunt Feedback 6248.7 The Voltage Regulator as a Feedback Circuit 6268.8 Feedback Circuit Analysis Using the Return Ratio 6328.8.1 Closed-Loop Gain Using the Return Ratio 6348.8.2 Closed-Loop Impedance Formula Using the Return Ratio 6408.8.3 Summary--Return-Ratio Analysis 6468.9 Modeling Input and Output Ports in Feedback Circuits 646Problems 649References 656Chapter 9 Frequency Response and Stability of Feedback Amplifiers 6579.1 Introduction 6579.2 Relation Between Gain and Bandwidth in Feedback Amplifiers 6579.3 Instability 6599.3.1 The Nyquist Criterion 6599.3.2 Phase Margin and Gain Margin 6619.3.3 Stability of the Super Source Follower 6669.4 Compensation 6719.4.1 Theory of Compensation 6719.4.2 Methods of Compensation 6769.4.3 Two-Stage MOS Amplifier Compensation 6819.4.4 Compensation of Single-Stage CMOS Op Amps 6939.4.5 Nested Miller Compensation 6969.5 Root-Locus Techniques 7059.5.1 Root Locus for a Three-Pole Transfer Function 7059.5.2 Rules for Root-Locus Construction 7089.5.3 Root Locus for Dominant-Pole Compensation 7189.5.4 Root Locus for Feedback-Zero Compensation 7199.6 Slew Rate 7239.6.1 Origin of Slew-Rate Limitations 7239.6.2 Methods of Improving Slew Rate in Two-Stage Op Amps 7259.6.3 Improving Slew Rate in Bipolar Op Amps 7289.6.4 Improving Slew Rate in MOS Op Amps 7299.6.5 Effect of Slew-Rate Limitations on Large-Signal Sinusoidal Performance 7339.7 Effect of Feedback on a Pole-Zero Doublet 734A.9.1 Analysis in Terms of Return-Ratio Parameters 736A.9.2 Roots of a Quadratic Equation 737Problems 739References 746Chapter 10 Nonlinear Analog Circuits 74710.1 Introduction 74710.2 Analog Multipliers Employing the Bipolar Transistor 74710.2.1 The Emitter-Coupled Pair as a Simple Multiplier 74810.2.2 The dc Analysis of the Gilbert Multiplier Cell 75010.2.3 The Gilbert Cell as an Analog Multiplier 75210.2.4 A Complete Analog Multiplier 75510.2.5 The Gilbert Multiplier Cell as a Balanced Modulator and Phase Detector 75610.3 Phase-Locked Loops 76010.3.1 Phase-Locked Loop Concepts 76010.3.2 The Phase-Locked Loop in the Locked Condition 76210.3.3 Integrated-Circuit Phase-Locked Loops 77110.4 Nonlinear Function Synthesis 775Problems 777References 779Chapter 11 Noise in Integrated Circuits 78111.1 Introduction 78111.2 Sources of Noise 78111.2.1 Shot Noise 78111.2.2 Thermal Noise 78511.2.3 Flicker Noise (1/f Noise) 78611.2.4 Burst Noise (Popcorn Noise) 78711.2.5 Avalanche Noise 78711.3 Noise Models of Integrated-Circuit Components 78911.3.1 Junction Diode 78911.3.2 Bipolar Transistor 79011.3.3 MOS Transistor 79111.3.4 Resistors 79811.3.5 Capacitors and Inductors 79911.4 Circuit Noise Calculations 79911.4.1 Bipolar Transistor Noise Performance 80211.4.2 Equivalent Input Noise and the Minimum Detectable Signal 80511.4.3 MOS Transistor Noise Performance 80711.5 Equivalent Input Noise Generators 81211.5.1 Bipolar Transistor Noise Generators 81311.5.2 MOS Transistor Noise Generators 81811.6 Effect of Feedback on Noise Performance 82011.6.1 Effect of Ideal Feedback on Noise Performance 82111.6.2 Effect of Practical Feedback on Noise Performance 82111.7 Noise Performance of Other Transistor Configurations 82811.7.1 Common-Base-Stage Noise Performance 82811.7.2 Emitter-Follower Noise Performance 82911.7.3 Differential-Pair Noise Performance 83011.7.4 Super-Source-Follower Noise Performance 83311.8 Noise in Operational Amplifiers 83611.9 Noise Bandwidth 84011.10 Noise Figure and Noise Temperature 84511.10.1 Noise Figure 84511.10.2 Noise Temperature 849Problems 849References 854Chapter 12 Fully Differential Operational Amplifiers 85712.1 Introduction 85712.2 Properties of Fully Differential Amplifiers 85712.3 Small-Signal Models for Balanced Differential Amplifiers 86012.4 Common-Mode Feedback 86512.4.1 Common-Mode Feedback at Low Frequencies 86712.4.2 Stability and Compensation Considerations in a CMFB Loop 87112.5 CMFB Circuits 87312.5.1 CMFB Using Resistive Divider and Amplifier 87312.5.2 CMFB Using Two Differential Pairs 87812.5.3 CMFB Using Transistors in the Triode Region 88012.5.4 Switched-Capacitor CMFB 88212.6 Fully Differential Op Amps 88512.6.1 A Fully Differential Two-Stage Op Amp 88512.6.2 Fully Differential Telescopic-Cascode Op Amp 89612.6.3 Fully Differential Folded-Cascode Op Amp 89712.6.4 A Differential Op Amp with Two Differential Input Stages 89812.6.5 Neutralization 89912.7 Unbalanced Fully Differential Circuits 90112.8 Bandwidth of the CMFB Loop 90712.9 Analysis of a CMOS Fully Differential Folded-Cascode Op Amp 90912.9.1 dc Biasing 91112.9.2 Low-Frequency Analysis 91412.9.3 Frequency and Time Responses in a Feedback Application 920Problems 927References 933Index 935