Master the art of FPGA digital system design with Verilog and VHDL

1 Introduction1.1 Hardware Description Languages1.2 FPGA Boards and Software Tools1.3 Topics to Be Covered in the Book2 Field-Programmable Gate Arrays2.1 A Brief Introduction to Digital Electronics2.1.1 Bit Values as Voltage Levels2.1.2 Transistor as a Switch2.1.3 Logic Gates from Switches2.2 FPGA Building Blocks2.2.1 Layout of the Xilinx Artix-7 XC7A35T FPGA2.2.2 Input/Output Blocks2.2.3 Configurable Logic Blocks2.2.4 Interconnect Resources2.2.5 Block RAM2.2.6 DSP Slices2.2.7 Clock Management2.2.8 The XADC Block2.2.9 High-Speed Serial I/O Transceivers2.2.10 Peripheral Component Interconnect Express Interface2.3 FPGA-Based Digital System Design Philosophy2.3.1 How to Think While Using FPGAs2.3.2 Advantages and Disadvantages of FPGAs2.4 Usage Areas of FPGAs2.5 Summary2.6 Exercises3 Basys3 and Arty FPGA Boards3.1 The Basys3 Board3.1.1 Powering the Board3.1.2 Input/Output3.1.3 Configuring the FPGA3.1.4 Advanced Connectors3.1.5 External Memory3.1.6 Oscillator/Clock3.2 The Arty Board3.2.1 Powering the Board3.2.2 Input/Output3.2.3 Configuring the FPGA3.2.4 Advanced Connectors3.2.5 External Memory3.2.6 Oscillator/Clock3.3 Summary3.4 Exercises4 The Vivado Design Suite4.1 Installation and the Welcome Screen4.2 Creating a New Project4.2.1 Adding a Verilog File4.2.2 Adding a VHDL File4.3 Synthesizing the Project4.4 Simulating the Project4.4.1 Adding a Verilog Testbench File4.4.2 Adding a VHDL Testbench File4.5 Implementing the Synthesized Project4.6 Programming the FPGA4.6.1 Adding the Basys3 Board Constraint File to the Project4.6.2 Programming the FPGA on the Basys3 Board4.6.3 Adding the Arty Board Constraint File to the Project4.6.4 Programming the FPGA on the Arty Board4.7 Vivado Design Suite IP Management4.7.1 Existing IP Blocks in Vivado4.7.2 Generating a Custom IP4.8 Application on the Vivado Design Suite4.9 Summary4.10 Exercises5 Introduction to Verilog and VHDL5.1 Verilog Fundamentals5.1.1 Module Representation5.1.2 Timing and Delays in Modeling5.1.3 Hierarchical Module Representation5.2 Testbench Formation in Verilog5.2.1 Structure of a Verilog Testbench File5.2.2 Displaying Test Results5.3 VHDL Fundamentals5.3.1 Entity and Architecture Representations5.3.2 Dataflow Modeling5.3.3 Behavioral Modeling5.3.4 Timing and Delays in Modeling5.3.5 Hierarchical Structural Representation5.4 Testbench Formation in VHDL5.4.1 Structure of a VHDL Testbench File5.4.2 Displaying Test Results5.5 Adding an Existing IP to the Project5.5.1 Adding an Existing IP in Verilog5.5.2 Adding an Existing IP in VHDL5.6 Summary5.7 Exercises6 Data Types and Operators6.1 Number Representations6.1.1 Binary Numbers6.1.2 Octal Numbers6.1.3 Hexadecimal Numbers6.2 Negative Numbers6.2.1 Signed Bit Representation6.2.2 One's Complement Representation6.2.3 Two's Complement Representation6.3 Fixed- and Floating-Point Representations6.3.1 Fixed-Point Representation6.3.2 Floating-Point Representation6.4 ASCII Code6.5 Arithmetic Operations on Binary Numbers6.5.1 Addition6.5.2 Subtraction6.5.3 Multiplication6.5.4 Division6.6 Data Types in Verilog6.6.1 Net and Variable Data Types6.6.2 Data Values6.6.3 Naming a Net or Variable6.6.4 Defining Constants and Parameters6.6.5 Defining Vectors6.7 Operators in Verilog6.7.1 Arithmetic Operators6.7.2 Concatenation and Replication Operators6.8 Data Types in VHDL6.8.1 Signal and Variable Data Types6.8.2 Data Values6.8.3 Naming a Signal or Variable6.8.4 Defining Constants6.8.5 Defining Arrays6.9 Operators in VHDL6.9.1 Arithmetic Operators6.9.2 Concatenation Operator6.10 Application on Data Types and Operators6.11 FPGA Building Blocks Used in Data Types and Operators6.11.1 Implementation Details of Vector Operations6.11.2 Implementation Details of Arithmetic Operations6.12 Summary6.13 Exercises7 Combinational Circuits7.1 Basic Definitions7.1.1 Binary Variable7.1.2 Logic Function7.1.3 Truth Table7.2 Logic Gates7.2.1 The NOT Gate7.2.2 The OR Gate7.2.3 The AND Gate7.2.4 The XOR Gate7.3 Combinational Circuit Analysis7.3.1 Logic Function Formation between Input and Output7.3.2 Boolean Algebra7.3.3 Gate-Level Minimization7.4 Combinational Circuit Implementation7.4.1 Truth Table-Based Implementation7.4.2 Implementing One-Input Combinational Circuits7.4.3 Implementing Two-Input Combinational Circuits7.4.4 Implementing Three-Input Combinational Circuits7.5 Combinational Circuit Design7.5.1 Analyzing the Problem to Be Solved7.5.2 Selecting a Solution Method7.5.3 Implementing the Solution7.6 Sample Designs7.6.1 Home Alarm System7.6.2 Digital Safe System7.6.3 Car Park Occupied Slot Counting System7.7 Applications on Combinational Circuits7.7.1 Implementing the Home Alarm System7.7.2 Implementing the Digital Safe System7.7.3 Implementing the Car Park Occupied Slot Counting System7.8 FPGA Building Blocks Used in Combinational Circuits7.9 Summary7.10 Exercises8 Combinational Circuit Blocks8.1 Adders8.1.1 Half Adder8.1.2 Full Adder8.1.3 Adders in Verilog8.1.4 Adders in VHD8.2 Comparators8.2.1 Comparators in Verilog8.2.2 Comparators in VHDL8.3 Decoders8.3.1 Decoders in Verilog8.3.2 Decoders in VHDL8.4 Encoders8.4.1 Encoders in Verilog8.4.2 Encoders in VHDL8.5 Multiplexers8.5.1 Multiplexers in Verilog8.5.2 Multiplexers in VHDL8.6 Parity Generators and Checkers8.6.1 Parity Generators8.6.2 Parity Checkers8.6.3 Parity Generators and Checkers in Verilog8.6.4 Parity Generators and Checkers in VHDL8.7 Applications on Combinational Circuit Blocks8.7.1 Improving the Calculator8.7.2 Improving the Home Alarm System8.7.3 Improving the Car Park Occupied Slot Counting System8.8 FPGA Building Blocks Used in Combinational Circuit Blocks8.9 Summary8.10 Exercises9 Data Storage Elements9.1 Latches9.1.1 SR Latch9.1.2 D Latch9.1.3 Latches in Verilog9.1.4 Latches in VHDL9.2 Flip-Flops9.2.1 D Flip-Flop9.2.2 JK Flip-Flop9.2.3 T Flip-Flop9.2.4 Flip-Flops in Verilog9.2.5 Flip-Flops in VHDL9.3 Register9.4 Memory9.5 Read-Only Memory9.5.1 ROM in Verilog9.5.2 ROM in VHDL9.5.3 ROM Formation Using IP Blocks9.6 Random Access Memory9.7 Application on Data Storage Elements9.8 FPGA Building Blocks Used in Data Storage Elements9.9 Summary9.10 Exercises10 Sequential Circuits10.1 Sequential Circuit Analysis10.1.1 Definition of State10.1.2 State and Output Equations10.1.3 State Table10.1.4 State Diagram10.1.5 State Representation in Verilog10.1.6 State Representation in VHDL10.2 Timing in Sequential Circuits10.2.1 Synchronous Operation10.2.2 Asynchronous Operation10.3 Shift Register as a Sequential Circuit10.3.1 Shift Registers in Verilog10.3.2 Shift Registers in VHDL10.3.3 Multiplication and Division Using Shift Registers10.4 Counter as a Sequential Circuit10.4.1 Synchronous Counter10.4.2 Asynchronous Counter10.4.3 Counters in Verilog10.4.4 Counters in VHDL10.4.5 Frequency Division Using Counters10.5 Sequential Circuit Design10.6 Applications on Sequential Circuits10.6.1 Improving the Home Alarm System10.6.2 Improving the Digital Safe System10.6.3 Improving the Car Park Occupied Slot Counting System10.6.4 Vending Machine10.6.5 Digital Clock10.7 FPGA Building Blocks Used in Sequential Circuits10.8 Summary10.9 Exercises11 Embedding a Soft-Core Microcontroller11.1 Building Blocks of a Generic Microcontroller11.1.1 Central Processing Unit11.1.2 Arithmetic Logic Unit11.1.3 Memory11.1.4 Oscillator/Clock11.1.5 General Purpose Input/Output11.1.6 Other Blocks11.2 Xilinx PicoBlaze Microcontroller11.2.1 Functional Blocks of PicoBlaze11.2.2 PicoBlaze in Verilog11.2.3 PicoBlaze in VHDL11.2.4 PicoBlaze Application on the Basys3 Board11.3 Xilinx MicroBlaze Microcontroller11.3.1 MicroBlaze as an IP Block in Vivado11.3.2 MicroBlaze MCS Application on the Basys3 Board11.4 Soft-Core Microcontroller Applications11.5 FPGA Building Blocks Used in Soft-Core Microcontrollers11.6 Summary11.7 Exercises12 Digital Interfacing12.1 Universal Asynchronous Receiver/Transmitter12.1.1 Working Principles of UART12.1.2 UART in Verilog12.1.3 UART in VHDL12.1.4 UART Applications12.2 Serial Peripheral Interface12.2.1 Working Principles of SPI12.2.2 SPI in Verilog12.2.3 SPI in VHDL12.2.4 SPI Application12.3 Inter-Integrated Circuit12.3.1 Working Principles of I2C12.3.2 I2C in Verilog12.3.3 I2C in VHDL12.3.4 I2C Application12.4 Video Graphics Array12.4.1 Working Principles of VGA12.4.2 VGA in Verilog12.4.3 VGA in VHDL12.4.4 VGA Application12.5 Universal Serial Bus12.5.1 USB-Receiving Module in Verilog12.5.2 USB-Receiving Module in VHDL12.5.3 USB Keyboard Application12.6 Ethernet12.7 FPGA Building Blocks Used in Digital Interfacing12.8 Summary12.9 Exercises13 Advanced Applications13.1 Integrated Logic Analyzer IP Core Usage13.2 The XADC Block Usage13.3 Adding Two Floating-Point Numbers13.4 Calculator13.5 Home Alarm System13.6 Digital Safe System13.7 Car Park Occupied Slot Counting System13.8 Vending Machine13.9 Digital Clock13.10 Moving Wave via LEDs13.11 Translator13.12 Air Freshener Dispenser13.13 Obstacle-Avoiding Tank13.14 Intelligent Washing Machine13.15 Non-Touch Paper Towel Dispenser13.16 Traffic Lights13.17 Car Parking Sensor System13.18 Body Weight Scale13.19 Intelligent Billboard13.20 Elevator Cabin Control System13.21 Digital Table Tennis Game13.22 Customer Counter13.23 Frequency Meter13.24 Pedometer14 What Is Next?14.1 Vivado High-Level Synthesis Platform14.2 Developing a Project in Vivado HLS to Generate IP14.3 Using the Generated IP in Vivado14.4 Summary14.5 ExercisesReferencesIndex