Routing Congestion in VLSI Circuits
-37 %

Routing Congestion in VLSI Circuits

Estimation and Optimization
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ISBN-13:
9780387300375
Erscheinungsdatum:
01.05.2007
Seiten:
248
Autor:
Prashant Saxena
Gewicht:
557 g
Format:
242x165x23 mm
Serie:
Series on Integrated Circuits and Systems
Sprache:
Englisch
Beschreibung:

This volume provides a complete understanding of the fundamental causes of routing congestion in present-day and next-generation VLSI circuits, offers techniques for estimating and relieving congestion, and provides a critical analysis of the accuracy and effectiveness of these techniques. The book includes metrics and optimization techniques for routing congestion at various stages of the VLSI design flow. The subjects covered include an explanation of why the problem of congestion is important and how it will trend, plus definitions of metrics that are appropriate for measuring congestion, and descriptions of techniques for estimating and optimizing routing congestion issues in cell-/library-based VLSI circuits.
This volume provides the reader with a complete understanding of the fundamental causes of routing congestion in present-day and next-generation VLSI circuits, techniques for estimating and relieving congestion, and a critical analysis of the accuracy and effectiveness of these techniques. Readers are supplied with the knowledge to prudently choose an approach that is appropriate to their design goals. The book includes metrics and optimization techniques for routing congestion at various stages of the VLSI design flow, including the architectural level, the logic synthesis/technology mapping level, the placement phase, and the routing phase. The subjects covered include an explanation of why the problem of congestion is important and how it will trend, plus definitions of metrics that are appropriate for measuring congestion, and descriptions of techniques for estimating and optimizing routing congestion issues in cell-/library-based VLSI circuits.
The Origins of Congestion.- An Introduction to Routing Congestion.- The Estimation of Congestion.- Placement-level Metrics for Routing Congestion.- Synthesis-level Metrics for Routing Congestion.- The Optimization of Congestion.- Congestion Optimization During Interconnect Synthesis and Routing.- Congestion Optimization During Placement.- Congestion Optimization During Technology Mapping and Logic Synthesis.- Congestion Implications of High Level Design.
This volume provides a complete understanding of the fundamental causes of routing congestion in present-day and next-generation VLSI circuits, offers techniques for estimating and relieving congestion, and provides a critical analysis of the accuracy and effectiveness of these techniques.

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