Beschreibung:
Functional Verification of Programmable Embedded Architectures: A Top-Down Approach is designed for students, researchers, CAD tool developers, designers, and managers interested in the development of tools, techniques and methodologies for system-level design, microprocessor validation, design space exploration and functional verification of embedded systems.
Includes the latest studies/statistics on both verification complexity and design failures
to Functional Verification.- Architecture Specification.- Architecture Specification.- Validation of Specification.- Top-Down Validation.- Executable Model Generation.- Design Validation.- Functional Test Generation.- Future Directions.- Conclusions.