Field Programmable Gate Arrays (FPGAs) are devices that provide a fast, low-cost way for embedded system designers to customize products and deliver new versions with upgraded features, because they can handle very complicated functions, and be reconfigured an infinite number of times. In addition to introducing the various architectural features available in the latest generation of FPGAs, The Design Warrior's Guide to FPGAs also covers different design tools and flows.This book covers information ranging from schematic-driven entry, through traditional HDL/RTL-based simulation and logic synthesis, all the way up to the current state-of-the-art in pure C/C++ design capture and synthesis technology. Also discussed are specialist areas such as mixed hardward/software and DSP-based design flows, along with innovative new devices such as field programmable node arrays (FPNAs). Clive "Max" Maxfield is a bestselling author and engineer with a large following in the electronic design automation (EDA)and embedded systems industry. In this comprehensive book, he covers all the issues of interest to designers working with, or contemplating a move to, FPGAs in their product designs. While other books cover fragments of FPGA technology or applications this is the first to focus exclusively and comprehensively on FPGA use for embedded systems.

Introductio; Fundamental Concepts; The Origin of FPGAs; Alternative FPGA Architectures; Programming (Configuring) an FPGA; Who Are All the Players?; FPGA Versus ASIC; HDL-Based Design Flows; Silicon Virtual Prototyping; C/C++ etc.-Based Design Flows;DSP-Based Design Flows; Embedded Processor-Based; Modular and Incremental Design; High-Speed Design and Other PCB Considerations; Observing Internal Nodes in an FPGA; Intellectual Property; Migrating ASIC Designs to FPGAs and Vice Versa; Simulation, Synthesis, Verification, etc.; Choosing the Right Device; Gigabit Transceivers; Reconfigurable Computing; Creating an Open-Source-BasedDesign Flow; Future FPGA Developments; Appendix A:Signal Integrity 101;Capacitive and inductive coupling(crosstalk), Chip-level effects, Board-level effects, The evolution of delay specifications; Appendix B: Deep-Submicron Delay Effects 101, A potpourri of definitions, Alternative interconnect models, DSM delay effectsSummary, The Ouroboras, Many-to-one implementations; Appendix C: Linear Feedback Shift Registers 101, More taps than you know what to do with, Seeding an LFSR, FIFO applications, Modifying LFSRs to sequence 2n values, Accessing the previous value, Encryption and decryption applications,Cyclic redundancy check applications.