Digital Logic Design and Computer Organization with Computer Architecture for Security provides practicing engineers and students with a clear understanding of computer hardware technologies. The fundamentals of digital logic design as well as the use of the Verilog hardware description language are discussed. The book covers computer organization and architecture, modern design concepts, and computer security through hardware.

1 Introduction1.1 Introduction1.1.1 Data Representation1.1.2 Data Path1.1.3 Computer Systems1.1.4 Embedded Systems1.2 Logic Design1.2.1 Circuit Minimization1.2.2 Implementation1.2.3 Types of Circuits1.2.4 Computer-Aided Design Tools1.3 Computer Organization1.4 Computer Architecture1.4.1 Pipelining1.4.2 Parallelism1.5 Computer SecurityReferencesExercises2 Combinational Circuits: Small Designs2.1 Introduction2.1.1 Signal Naming Standards2.2 Logic Expressions2.2.1 Sum of Product Expression2.2.2 Product of Sum Expression2.3 Canonical Expression2.3.1 Min-Terms2.3.2 Max-Terms2.4 Logic Minimization2.4.1 Karnaugh Map2.4.2 K-Map Minimization2.5 Logic Minimization Algorithm2.5.1 Minimization Software2.6 Circuit Timing Diagram2.6.1 Signal Propagation Delay2.6.2 Fan-In and Fan-Out2.7 Other Gates2.7.1 Buffer2.7.2 Open Collector Buffer2.7.3 Tri-State Buffer2.8 Design Examples2.8.1 Full Adder2.8.2 Multiplexer2.8.3 Decoder2.8.4 Encoder2.9 Implementation2.9.1 Programmable Logic Devices2.9.2 Design Flow2.10 Hardware Description Languages2.10.1 Structural Model2.10.2 Propagation Delay Simulation2.10.3 Behavioral Modeling2.10.4 Synthesis and SimulationReferencesExercises3 Combinational Circuits: Large Designs3.1 Introduction3.1.1 Top-Down Design Methodology3.2 Arithmetic Functions3.3 Adder3.3.1 Carry Propagate Adder3.3.2 Carry Look-Ahead Adder3.4 Subtractor3.5 2's Complement Adder/Subtractor3.6 Arithmetic Logic Unit3.6.1 Design Partitioning: Bit-Parallel3.6.2 Design Partitioning: Bit-Serial3.7 Design Examples3.7.1 Multiplier3.7.2 Divider3.8 Real Number Arithmetic3.8.1 Floating-Point Standards3.8.2 Floating-Point Data Space3.8.3 Floating-Point Arithmetic3.8.4 Floating-Point UnitReferencesExercises4 Sequential Circuits: Core Modules4.1 Introduction4.2 SR Latch4.2.1 Clocked SR Latch4.3 D-Latch4.4 Disadvantage of Latches4.5 D Flip-Flop4.5.1 Alternative Circuit4.5.2 Operating Conventions4.5.3 Setup and Hold Times4.6 Clock Frequency Estimation without Clock Skew4.7 Flip-Flop with Enable4.8 Other Flip-Flops4.9 Hardware Description Language ModelsReferencesExercises5 Sequential Circuits: Small Designs5.1 Introduction5.2 Introduction to FSM: Register Design5.2.1 Register Model5.2.2 Multifunction Registers5.3 Finite State Machine Design5.3.1 Binary Encoded States5.3.2 One-Hot Encoded States5.4 Counters5.5 Fault-Tolerant Finite State Machine5.5.1 Hamming Coding Scheme5.6 Sequential Circuit Timing5.6.1 Clock Frequency Estimation with Clock Skew5.6.2 Asynchronous Interface5.7 Hardware Description Language Models5.7.1 Synthesis and SimulationReferencesExercises6 Sequential Circuits: Large Designs6.1 Introduction6.1.1 Register Transfer Notation6.2 Data Path Design6.2.1 Single-Cycle6.2.2 Multicycle6.2.3 Pipelined6.3 Control Unit Design Techniques6.3.1 Hardwired Control: FSD6.3.2 Microprogrammed Control6.3.3 Hardwire Control: Pipeline6.4 Energy and Power Consumption6.5 Design Examples6.5.1 Unsigned Sequential Multiplier6.5.2 Signed Sequential Multiplier6.5.3 Computer Graphics: RotationReferencesExercises7 Memory7.1 Introduction7.2 Memory Technologies7.2.1 Read-Only Memories7.2.2 Random Access Memories7.2.3 Applications7.3 Memory Cell Array7.3.1 Word Access7.3.2 Burst Access7.4 Memory Organization7.4.1 Modern DRAMs7.4.2 SRAM Cell Model7.4.3 Internal Organization: SRAM Chip7.4.4 Memory Unit Design7.5 Memory Timing7.5.1 SRAM7.5.2 DRAM7.5.3 SDRAM7.5.4 DDR SDRAM7.6 Memory Architecture7.6.1 High-Order Interleaving7.6.2 Low-Order Interleaving7.6.3 Multichannel7.7 Design Example: Multiprocessor Memory Architecture7.7.1 UMA versus NUMA7.7.2 A NUMA Application7.8 HDL ModelsReferencesExercises8 Instruction Set Architecture8.1 Introduction8.1.1 Type of Instructions8.1.2 Program Translation8.1.3 Instruction Cycle8.2 Types of Instruction Set Architecture8.2.1 Addressing Modes8.2.2 Instruction Format8.2.3 Stack-ISA8.2.4 Accumulator-ISA8.2.5 CISC-ISA8.2.6 RISC-ISA8.3 Design Example8.3.1 Acc-ISA Instruction Set Design8.3.2 Acc-ISA Processor: Single-Cycle8.3.3 Acc-ISA Processor: Pipelined8.3.4 RISC-ISA Processor8.4 Advanced Processor Architectures8.4.1 Deep Pipelining8.4.2 Branch Prediction8.4.3 Instruction-Level Parallelism8.4.4 MultithreadingReferencesExercises9 Computer Architecture: Interconnection9.1 Introduction9.1.2 Interconnection Architectures9.2 Memory Controller9.2.1 Simple Memory Controller9.2.2 Modern Memory Controller9.3 I/O Peripheral Devices9.4 Controlling and Interfacing I/O Devices9.4.1 I/O Ports9.5 Data Transfer Mechanisms9.5.1 Interrupt-Driven Transfer9.5.2 Programmed Transfer9.5.3 DMA Transfer9.6 Interrupts9.6.1 Handling Interruptions9.6.2 Interrupt Structures9.7 Design Example: Interrupt Handling CPU9.8 USB Host Controller Interface9.8.1 Standards9.8.2 Transactions9.8.3 Transfers9.8.4 Descriptors9.8.5 Frames9.8.6 Transaction Organization9.8.7 Transaction ExecutionReferencesExercises10 Memory System10.1 Introduction10.1.1 Memory Hierarchy10.2 Cache Mapping10.2.1 Direct Mapping10.2.2 Types of Cache Misses10.2.3 Set-Associative Mapping10.3 Cache Coherency10.3.1 Invalidation versus Update Protocols10.3.2 Snoop Cache Coherence Protocol10.3.3 Write-Through Protocol10.3.4 Write-Back Protocols10.4 Virtual Memory10.4.1 Virtual Address Translation10.4.2 Translation Lookaside Buffer10.4.3 Processor OrganizationReferencesExercises11 Computer Architecture: Security11.1 Introduction11.1.1 Security Engineering Methodology11.1.2 Threat Classes11.1.3 Access Control and Types11.1.4 Security Policy Models11.1.5 Attack Classes11.2 Hardware Backdoor Attacks11.2.1 Data and Control Attacks11.2.2 Timer Attack11.2.3 Security Policy Mechanisms11.3 Software/Physical Attacks11.3.1 Spoofing11.3.2 Splicing11.3.3 Replay11.3.4 Man-in-the-Middle11.4 Trusted Computing Base11.5 Cryptography11.5.1 Symmetric-Key Ciphers11.5.2 Modes of Operation11.5.3 Asymmetric-Key Ciphers11.6 Hashing11.7 Cryptography Hash11.7.1 Message Authentication Code11.7.2 Hash MAC11.8 Storing Cryptography Keys through Hardware11.8.1 Keychain Organization11.8.2 Storage and Access11.8.3 Application Example: Keychain as Access Control11.9 Hash Tree11.9.1 Application Example: Keychain Authentication11.9.2 Application Example: Memory Authentication11.10 Secure Coprocessor Architecture11.10.1 Trusted Platform Module11.11 Secure Processor Architecture11.11.1 Program Code Integrity11.11.2 Operational Security Mechanisms11.11.3 Program Code Confidentiality11.11.4 Program Code Integrity and Confidentiality11.11.5 Program Data Integrity11.11.6 Program Data Confidentiality11.11.7 Program Data Integrity and Confidentiality11.11.8 Program Code and Data Integrity and Confidentiality11.11.9 Handling Interruption11.12 Design Example: Secure Processor11.12.1 SP Specification11.12.2 Processor Architecture11.12.3 Encryption Decryption Hashing Engine11.12.4 Hash Tree Engine11.13 Further ReadingReferencesExercisesBibliographyIndex